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| ICX412AQF Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras Description The ICX412AQF is a diagonal 8.933mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Sensitivity, saturation signal, smear and frame rate have been improved compared to the ICX252AQF. This chip features an electronic shutter with variable charge-storage time. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. 20 pin SOP (Plastic) Pin 1 Features * Supports frame readout * High horizontal and vertical resolution * Supports high frame rate readout mode: 30 frames/s, AF1 mode: 60 frames/s, 50 frames/s, AF2 mode: 120 frames/s, 100 frames/s * Square pixel * Horizontal drive frequency: 22.5MHz * No voltage adjustments (reset gate and substrate bias are not adjusted.) * R, G, B primary color mosaic filters on chip * High sensitivity, low dark current * Continuous variable-speed shutter * Excellent anti-blooming characteristics * Exit pupil distance recommended range -20 to -100mm * 20-pin high-precision plastic package 2 V 8 4 Pin 11 H 48 Optical black position (Top View) Device Structure * Interline CCD image sensor * Total number of pixels: 2140 (H) x 1560 (V) approx. 3.34M pixels * Number of effective pixels: 2088 (H) x 1550 (V) approx. 3.24M pixels * Number of active pixels: 2080 (H) x 1542 (V) approx. 3.21M pixels diagonal 8.933mm * Number of recommended recording pixels: 2048 (H) x 1536 (V) approx. 3.15M pixels diagonal 8.832mm aspect ratio 4:3 * Chip size: 8.10mm (H) x 6.64mm (V) * Unit cell size: 3.45m (H) x 3.45m (V) * Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels * Number of dummy bits: Horizontal 28 Vertical 1 (even fields only) * Substrate material: Silicon Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E01657-PS ICX412AQF Block Diagram and Pin Configuration (Top View) TEST TEST VOUT GND V1B V1A V3B V3A 2 B Gr B Gr B Gr Note) V2 10 9 8 7 6 5 4 3 Gb B Gr B Gr B Gr Gb R Gb R Gb R Vertical register R Gb R Gb R Horizontal register Note) : Photo sensor 11 12 13 14 15 16 17 18 19 20 H2 H1 VL H1 RG VDD Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol V4 V3A V3B V2 V1A V1B TEST TEST GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Test pin1 Test pin1 GND Signal output Pin No. 11 12 13 14 15 16 17 18 19 20 Symbol VDD RG H2 H1 GND SUB CSUB VL H1 H2 Description Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock GND Substrate clock Substrate bias2 Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock 1 Leave this pin open 2 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1F. SUB CSUB GND -2- H2 V4 1 ICX412AQF Absolute Maximum Ratings Item VDD, VOUT, RG - SUB V1A, V1B, V3A, V3B - SUB Against SUB V2, V4, VL - SUB H1, H2, GND - SUB CSUB - SUB VDD, VOUT, RG, CSUB - GND Against GND V1A, V1B, V2, V3A, V3B, V4 - GND H1, H2 - GND Against VL V1A, V1B, V3A, V3B - VL V2, V4, H1, H2, GND - VL Voltage difference between vertical clock input pins Between input clock pins H1 - H2 H1, H2 - V4 Storage temperature Guaranteed temperature of performance Operating temperature 1 +24V (Max.) when clock width < 10s, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. Ratings -40 to +12 -50 to +15 -50 to +0.3 -40 to +0.3 -25 to -0.3 to +22 -10 to +18 -10 to +6.5 -0.3 to +28 -0.3 to +15 to +15 -6.5 to +6.5 -10 to +16 -30 to +80 -10 to +60 -10 to +75 Unit V V V V V V V V V V V V V C C C 1 Remarks -3- ICX412AQF Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 14.55 Typ. 15.0 1 2 2 Max. 15.45 Unit V Remarks 1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. 5.5 Typ. 7.5 Max. 9.5 Unit mA Remarks Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL VH Horizontal transfer clock voltage VHL VCR VRG Reset gate clock voltage VRGLH - VRGLL VRGL - VRGLm Substrate clock voltage VSUB 21.5 22.5 4.0 -0.05 0.8 3.0 5.0 0 2.5 3.3 5.25 0.4 0.5 23.5 Min. 14.55 -0.05 -0.2 -8.0 6.8 -0.25 -0.25 Typ. 15.0 0 0 -7.5 7.5 Max. Unit 15.45 0.05 0.05 -7.0 8.05 0.1 0.1 0.8 0.9 0.9 0.8 5.25 0.05 V V V V V V V V V V V V V V V V V V Waveform Diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 Low-level coupling Low-level coupling Cross-point voltage High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks -4- ICX412AQF Clock Equivalent Circuit Constants Item Capacitance between vertical transfer clock and GND Symbol CV1A, CV3A CV1B, CV3B CV2, CV4 CV1A2, CV3A4 CV1B2, CV3B4 CV23A, CV41A CV23B, CV41B Capacitance between vertical transfer clocks CV1A3A CV1B3B CV1A3B, CV1B3A CV24 CV1A1B, CV3A3B Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor CH1, CH2 CHH CRG CSUB R1A, R1B, R2, R3A, R3B, R4 RGND RH Min. Typ. 1500 5600 2700 390 470 120 180 39 220 62 75 68 36.5 88.5 8 1000 62 18 15 Max. Unit Remarks pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF V2 R2 CV1A3A CV23B CV23A V3A R3A CV2 CV3A CV3A3B CV1A3B CV3B CV3A4 R3B V3B CV3B4 R4 CV24 V1A R1A CV1B2 CV1A CV1A1B CV1B3A CV1B CV41A V1B R1B CV4 CV41B RGND CV1B3B CV1A2 RH H1 RH H1 CHH RH H2 RH H2 CH1 CH2 V4 Vertical transfer clock equivalent circuit -5- Horizontal transfer clock equivalent circuit ICX412AQF Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% M VVT 10% 0% tr twh tf 0V M 2 (2) Vertical transfer clock waveform V1A, V1B V3A, V3B VVH1 VVHH VVH VVHL VVHH VVHL VVHL VVHH VVHL VVHH VVH VVH3 VVL1 VVLH VVL3 VVLH VVLL VVL VVLL VVL V2 V4 VVHH VVHH VVH VVHL VVH VVHH VVHH VVH2 VVHL VVHL VVH4 VVHL VVL2VVLH VVLL VVL4 VVLH VVLL VVL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) -6- ICX412AQF (3) Horizontal transfer clock waveform tr H2 90% VCR VH VH 2 10% H1 two VHL twh tf twl Cross-point voltage for the H1 rising side of the horizontal transfer clocks H1 and H2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. (4) Reset gate clock waveform tr twh tf RG waveform VRGH twl VRG Point A VRGLH VRGLL VRGLm VRGL VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval with twh, then: VRG = VRGH - VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% M VSUB 10% VSUB 0% (A bias generated within the CCD) M 2 tf tr twh -7- ICX412AQF Clock Switching Characteristics (Horizontal drive frequency: 22.5MHz) twh Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1A, V1B, V2, V3A, V3B, V4 H1 H2 12 12 6 16 16 8 12 12 16 16 31 6.5 10.5 6.5 10.5 3 0.5 twl tr tf Unit s 350 6.5 10.5 6.5 10.5 3 0.5 ns Remarks During readout When using CXD3400N Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.63 2.83 0.5 15 0.5 ns tf tr - 2ns ns s During drain charge Reset gate clock RG Substrate clock SUB 2.5 3.02 Item Horizontal transfer clock Symbol H1, H2 two Min. Typ. Max. 10 16 Unit ns Remarks Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G 0.9 0.8 B 0.7 R Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0 400 450 500 550 Wave Length [nm] 600 650 700 -8- ICX412AQF Image Sensor Characteristics (horizontal drive frequency: 22.5MHz) Item G Sensitivity Sensitivity comparison Saturation signal Smear Video signal shading Dark signal Dark signal shading Line crawl G Line crawl R Line crawl B Lag R B Symbol Sg Rr Rb Vsat Sm SHg Vdt Vdt Lcg Lcr Lcb Lag Min. 364 0.4 0.35 500 -92 -82.5 -84 -74.5 20 25 10 5 3.8 3.8 3.8 0.5 Typ. 455 Max. 546 0.7 0.65 mV dB % mV mV % % % % Unit mV Measurement method 1 1 1 2 3 4 5 6 7 7 7 8 Ta = 60C (Ta = 25C) Remarks 1/30s accumulation Frame readout mode1 High frame rate readout mode Zone 0 and I Zone 0 to II' Ta = 60C, 5.0 frame/s Ta = 60C, 5.0 frame/s, 2 1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. 2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 2088 (H) 4 4 4 H 8 V 10 H 8 1550 (V) Zone 0, I Zone II, II' V 10 4 Ignored region Effective pixel region Measurement System CCD signal output [A] CCD C.D.S AMP S/H Gr/Gb channel signal output [B] S/H R/B channel signal output [C] Note) Adjust the amplifier gain so that the gain between [A] and [B], and between [A] and [C] equals 1. -9- ICX412AQF Image Sensor Characteristics Measurement Method Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. In addition, VSUB Cont. is turned off. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Color coding of this image sensor & Readout B2 Gb R B1 Gb R B Gr B Gr Gb R Gb R B Gr B Gr A1 A2 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For frame readout, the A1 and A2 lines are output as signals in the A field, and the B1 and B2 lines in the B field. Horizontal register Color Coding Diagram - 10 - ICX412AQF Readout modes 1. Readout modes list The following readout modes are possible by driving the image sensor at the timing specifications noted in this Data Sheet. Mode name Frame readout mode High frame rate readout mode AF1 mode AF2 mode NTSC mode PAL mode NTSC mode PAL mode NTSC mode PAL mode NTSC mode PAL mode Frame rate 5.0 frame/s 5.0 frame/s 30 frame/s 25 frame/s 60 frame/s 50 frame/s 120 frame/s 100 frame/s Number of effective output lines 1550 (Odd 775, Even 775) 1550 (Odd 775, Even 775) 258 258 117 145 33 47 2. Frame readout mode, high frame rate readout mode Frame readout mode 1st field 13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr VOUT 13 12 11 10 9 8 7 6 5 4 3 2 1 2nd field R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr High frame rate readout mode 13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT R Gb R Gb R Gb R Gb R Gb R Gb R Gr B Gr B Gr B Gr B Gr B Gr B Gr Note) Blacked out portions in the diagram indicate pixels which are not read out. 1. Frame readout mode In this mode, all pixel signals are divided into two fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode Output is performed at 30 frames per second by reading out 4 pixels for every 12 vertical pixels and adding 2 pixels in the horizontal CCD. The number of output lines is 258 lines. This readout mode emphasizes processing speed over vertical resolution. - 11 - ICX412AQF 3. AF1 mode, AF2 mode The AF modes increase the frame rate by cutting out a portion of the picture through high-speed elimination of the top and bottom of the picture in high frame rate readout mode. AF1 allows 1/60s and 1/50s output, and AF2 allows 1/120s and 1/100s output, so these modes are effective for raising the auto focus (AF) speed. In addition, it differs from the ICX252AQ, the output line position and number of output lines are fixed. See the timing specifications for the cut-out region. Top frame shift region Cut-out region Number of effective lines in high frame rate readout mode 258 Bottom high-speed sweep region - 12 - ICX412AQF Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. (3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance -33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diagram. 1. G Sensitivity, sensitivity comparison Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGR, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Sg = VG x 100 [mV] 30 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. Sm = 20 x log Vsm / ( Gra + Gba + Ra + Ba 1 1 x 500 x 4 10 ) [dB] (1/10V method conversion value) - 13 - ICX412AQF 4. Video signal shading Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value (Grmax [mV]) and minimum value (Grmin [mV]) of the Gr signal output and substitute the values into the following formula. SHg = (Grmax - Grmin)/150 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Line crawl Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (Glr, Glg, Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = Gli x 100 [%] (i = r, g, b) Gai 8. Lag Adjust the Gr signal output value generated by the strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) x 100 [%] VD V1A/V1B Light Strobe light timing Gr signal output 150mV Vlag (lag) Output - 14 - ICX412AQF Drive Circuit 3.3V -7.5V 15V 0.1 1 XSUB XV3 XSG3B XSG3A XV1 XSG1B XSG1A XV4 XV2 2 3 4 5 CXD3400N 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 100k 1/35V 0.1 0.1 2SC4250 1 V4 2 V3A 3 V3B 4 V2 5 V1A 6 V1B 7 TEST 8 TEST 9 10 GND VOUT CCD OUT 4.7k ICX412 (BOTTOM VIEW) VR1 (10k) SUB CSUB GND RG VL 3.3/20V VDD H2 H1 H1 H2 VSUB Cont. 0.01 20 19 18 17 16 15 14 13 12 11 H2 H1 RG 0.1 Substrate bias control signal VSUB Cont. 0.1 1M 3.3/16V 0.1 Mechanical shutter mode GND tr 2ms Internally generated value VSUB tf 10ms Substrate bias SUB pin voltage Notes) Substrate bias control 1. The saturation signal level decreases when exposure is performed using the mechanical shutter, so control the substrate bias. 2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting a 10k grounding registor to the CCD CSUB pin. Drive timing precautions 1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter, so do not ground the connected 10k resistor. 2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the substrate bias control signal is not set to high level 20ms before entering the exposure period and the 10k resistor connected to the CSUB pin is not grounded. 3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing two fields or more of idle transfer through vertical register high-speed sweep transfer from the time the mechanical shutter closes until sensor readout is performed. However, note that the VL potential and the SUB pin DC voltage sag at this time. - 15 - Drive Timing Chart (Vertical Sequence) Act. High frame rate readout mode High Frame Rate Readout Mode Frame Readout Mode/Electronic Shutter Normal Operation Exposure operation Frame readout mode High frame rate readout mode VD V1A V1B V2 V3A - 16 - V3B V4 SUB A B C D E F TRG Mechanical shutter VSUB Cont. CCD OUT A signal output B signal output C signal output D signal output (ODD) D signal output (EVEN) Output after frame readout OPEN CLOSE OPEN E signal output F signal output ICX412AQF Note) The B and C output signals contain a blooming component and should therefore not be used. Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error. Drive Timing Chart (Vertical Sync) NTSC/PAL Frame Readout Mode NTSC: 5.0 frame/s, PAL: 5.0 frame/s All pixels output period Exposure period VD HD 1 9 10 NTSC PAL "c" V1A/B V2 "a" "c" "b" V3A/B V4 SUB TRG Mechanical shutter VSUB Cont. OPEN CLOSE 1770 1772 1 1 94 97 98 102 102 876 876 885 886 886 887 894 895 895 896 979 980 981 982 983 984 987 988 1761 1762 1 9 10 94 97 98 1 3 5 7 1 3 5 7 9 11 1547 1549 2 4 6 8 2 4 6 8 10 12 CCD OUT 1548 1550 - 17 - OPEN ICX412AQF Note) 2544H, However, 886H and 1772H in NTSC mode are 810clk, 885H and 1770H in PAL mode are 1104clk. Drive Timing Chart (Readout) "a" Enlarged H1 2544 1 NTSC/PAL Frame Readout Mode NTSC: #97 PAL : #97 2544 1 428 52 52 NTSC: #98 PAL : #98 428 1272 1348 1366 V1A/B V2 V3A/B 1310 V4 "b" Enlarged H1 2544 1 52 NTSC: #982 PAL : #981 2544 1 428 52 NTSC: #983 PAL : #982 428 - 18 - 1196 V1A/B 1310 V2 1272 1348 V3A/B 1158 1234 V4 ICX412AQF Drive Timing Chart (High-speed Sweep Operation) "c" Enlarged NTSC/PAL Frame Readout Mode 239136clk = 94 line HD 52 1 52 V1A/B V2 - 19 - V3A/B V4 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 #1 #2 #3 #4 #1560 Note) In the period of high-speed sweep operation, the rising of input clock XV1A/B, XV2, XV3A/B and XV4 to vertical transfer clock driver CXD3400N should be delayed by 1 clock against the above timing chart. ICX412AQF Drive Timing Chart (Horizontal Sync) NTSC/PAL Frame Readout Mode Ignored pixel 4 bits 48 bits after horizontal sync 2544 1 5 Ignored pixel 4 bits 4 bits before horizontal sync 428 456 28 465 CLK 1 1 48 1 52 RG SHP SHD 1 110 1 1 186 1 1 190 1 1 190 1 38 114 114 114 1 76 1 152 V1A/B V2 V3A/B 1 72 V4 1 148 H1 H2 1 68 1 308 SUB 376 1 - 20 - ICX412AQF Drive Timing Chart (Vertical Sync) NTSC/PAL High Frame Rate Readout Mode NTSC: 30 frame/s, PAL: 25 frame/s VD HD 255 255 260 260 343 287 1 1 9 10 15 255 255 260 260 343 287 1 1 9 10 NTSC PAL 9 10 15 9 10 "d" V1A "d" V1B V2 V3A V3B V4 1527 1534 1539 1546 1527 1534 1539 1546 6 3 10 15 22 27 34 1525 1532 1537 1544 1549 1525 1532 1537 1544 1549 4 1 8 13 20 25 32 Note) 2624fH, However, 286H and 287H in NTSC mode are 1455clk, 343H in PAL mode is 2592clk. 4 1 8 13 20 25 32 CCD OUT 6 3 10 15 22 27 34 15 15 - 21 - ICX412AQF Drive Timing Chart (Readout) "d" Enlarged #1 H1 1 52 NTSC/PAL High Frame Rate Readout Mode #2 1 428 52 NTSC 2624 PAL 2624 1462 1538 NTSC 1455 PAL 2592 V1A 1196 1348 1592 1640 V1B 1310 1424 1624 1672 V2 1272 1348 V3A 1158 1386 1576 1656 V3B 1234 1500 1608 1688 V4 428 - 22 - ICX412AQF Drive Timing Chart (Horizontal Sync) NTSC/PAL High Frame Rate Readout Mode, AF1 Mode, AF2 Mode Ignored pixel 4 bits 48 bits after horizontal sync 2624 1 5 124 140 156 172 188 204 220 236 252 268 284 300 316 332 348 364 380 396 412 428 444 460 476 492 508 Ignored pixel 4 bits 4 bits before horizontal sync 536 28 545 CLK 1 1 48 1 52 RG SHP SHD V1A/B V2 V3A/B V4 H1 H2 1 68 1 388 SUB 456 1 - 23 - ICX412AQF Drive Timing Chart (Vertical Sync) NTSC/PAL AF1 Mode NTSC: 60 frame/s, PAL: 50 frame/s VD HD 170 142 159 131 170 142 172 144 1 1 159 131 172 144 1 1 12 15 12 12 NTSC PAL 12 15 "f" V1A High-speed sweep period 11H V1B "d" "e" "f" "d" "e" Frame shift period 10H V2 V3A V3B V4 AF1 mode output signal 1112 1114 1117 1119 1112 1114 1117 1119 423 430 435 442 423 421 423 421 6 6 421 428 433 440 4 1280 1282 1285 1287 423 430 435 442 CCD OUT 6 1280 1282 1285 1287 421 428 433 440 4 4 PAL 6 4 NTSC 15 9 9 15 9 9 - 24 - ICX412AQF Note) 2624fH, However, 143H and 144H in NTSC mode are 1383clk, 172H in PAL mode is 1296clk. Drive Timing Chart (Vertical Sync) NTSC/PAL AF2 Mode NTSC: 120 frame/s, PAL: 100 frame/s VD HD 71 72 1 84 71 72 1 19 22 54 19 19 NTSC PAL 19 22 68 85 86 1 68 85 86 1 "h" V1A High-speed sweep period 17H V1B "d" "g" "h" "d" "g" Frame shift period 17H V2 V3A V3B V4 AF2 mode output signal 675 682 687 694 862 867 862 867 675 673 675 673 6 6 4 673 680 685 692 CCD OUT 6 946 951 860 865 860 865 4 944 949 673 680 685 692 944 949 4 PAL 675 682 687 694 946 951 6 4 NTSC 22 9 9 22 9 9 - 25 - ICX412AQF Note) 2624fH, However, 72H in NTSC mode is 1384clk, and 86H in PAL mode is 1960clk. The frame rate in NTSC mode is longer than 1/120s by 0.15clk. Drive Timing Chart (High-speed Frame Shift Operation) "e" Enlarged AF1 mode 10 lines AF2 mode 17 lines HD 52 1 68 NTSC/PAL AF1 Mode, AF2 Mode 52 V1A/B 48 80 48 80 48 80 100 V2 48 80 48 80 48 80 - 26 - V3A/B 48 80 48 80 48 80 V4 84 48 80 48 80 48 80 #1 #2 AF1 mode #68 AF2 mode #110 ICX412AQF Drive Timing Chart (High-speed Sweep Operation) "f" Enlarged AF1 mode 11 lines AF2 mode 17 lines HD 52 1 68 NTSC/PAL AF1 Mode, AF2 Mode 52 V1A/B 48 80 48 80 48 80 100 V2 48 80 48 80 48 80 - 27 - V3A/B 48 80 48 80 48 80 V4 84 48 80 48 80 48 80 #1 #2 AF1 mode #75 AF2 mode #116 ICX412AQF ICX412AQF Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N Plactic package Compressive strength 50N 1.2Nm Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 28 - ICX412AQF c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength are the same. Structure A Package Chip Metal plate (lead frame) Structure B Cross section of lead frame The cross section of lead frame can be seen on the side of the package for structure A. - 29 - Package Outline Unit: mm 20 pin SOP A 6.9 2.5 0.25 (0.6) D 11 20 11 1.7 20 ~ 14.0 0.15 B 2.5 9.0 12.0 0.1 C 1.7 10.9 ~ 6.0 V H 1 12.7 13.8 0.1 10 0 to 10 0.15 1.7 1.7 0.5 0.8 10 1 B' 1.0 0.1 0.8 0.5 10.0 2.5 ~ 2.4 2.9 0.15 - 30 - PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL Sony Corporation 1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (6.9, 6.0) 0.075mm. 5. The rotation angle of the effective image area relative to H and V is 0.7. 1.27 0.3 M 0.3 PACKAGE STRUCTURE Plastic GOLD PLATING 42 ALLOY 0.95g AS-B7-03(E) 6. The height from the bottom "C" to the effective image area is 1.41 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.49 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 50m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 50m. 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. PACKAGE MASS DRAWING NUMBER ICX412AQF |
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